|Title of host publication||2nd Annual IEEE Northeast Workshop on Circuits and Systems, Montreal, Canada|
|Publisher or commissioning body||Institute of Electrical and Electronics Engineers (IEEE)|
|Pages||257 - 260|
|Number of pages||4|
|State||Published - Jun 2004|
|Conference||2nd IEEE Northeast Workshop on Circuits and Systems|
|Period||1/06/04 → …|
In this paper, we propose a 3D bus architecture as a processor-memory interconnection system to increase the throughput of the memory system currently used on line cards. The 3D bus architecture allows multiple processing elements on a line card to access a shared memory. The main advantage of the proposed architecture is to increase the network processor off-chip memory bandwidth while diminishing the latency otherwise caused by the single bus competition.
Conference Proceedings/Title of Journal: 2nd Annual IEEE Northeast Workshop on Circuits and Systems
Conference Organiser: IEEE
Rose publication type: Conference contribution
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2nd IEEE Northeast Workshop on Circuits and Systems
|Duration||1 Jun 2004 → …|