|Title of host publication||International Conference on Field Programmable Logic and Applications, 2009 (FPL 2009), Prague|
|Publisher or commissioning body||Institute of Electrical and Electronics Engineers (IEEE)|
|Pages||26 - 31|
|Number of pages||6|
|State||Published - Aug 2009|
|Event||International Conference on Field Programmable Logic and Applications - Prague, Czech Republic|
|Conference||International Conference on Field Programmable Logic and Applications|
|Period||1/08/09 → …|
Biophysically accurate neuron models have emerged as a very useful tool for neuroscience research. These models are based on solving differential equations that govern membrane potentials and spike generation. The level of detail that needs to be presented in the model to accurately emulate the behaviour of an organic cell is still an open question, although the timing of the spikes is considered to convey essential information. Models targeting hardware are traditionally based on fixed point implementations and low precision algorithms which incur a significant loss of information. This, in turn, could affect the functionality of a bioelectronic neuroprocessor in an undefined way. In this paper, a 32-bit floating point reconfigurable somatic neuroprocessor is presented targeting an FPGA device for real-time processing. For each individual neuron, the dynamics of ionic channels are described by a set of first order kinetic equations. A dedicated CORDIC unit is developed to solve the nonlinear functions that regulate spike generation. The results have been verified using an experimental setup that combines an FPGA device and a digital-to-analogue converter.
Rose publication type: Conference contribution
Additional information: With accompanying conference presentation
Sponsorship: Sponsor acknowledgments for Oversea Research Student Award (ORSAS) and Postgraduate Research Award of University of Bristol and funding supplied by the Micron Foundation (USA)
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- neuroprocessor, floating point, neuron models
International Conference on Field Programmable Logic and Applications
|Duration||1 Aug 2009 → …|