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A RAM based architecture for the implementation of bit-serial digital filters

Research output: Contribution to conferenceAbstract

Original languageEnglish
Publication dateNov 1992
Pages6/1 - 6/8
StatePublished

Abstract

Bit-serial implementations of digital signal processing algorithms often find favour where reduced implementation area is an important design criterion since they facilitate an efficient trade-off between silicon area and data throughput. Area-wise the adoption of a bit-serial regime not only offers single wire communication paths, but also allows the use of one-bit arithmetic operators. This paper presents a methodology and architecture which will facilitate the adoption of standard RAM compiled cells for bit serial digital filtering. The paper presents the method and general architecture, and describes a design which has been realised using this technique based on the Xilinx 4000 series FPGA. Finally, complexity comparisons are made between the new and conventional approaches

Additional information

Name of Conference: 12th Saraga Colloquium on Digital and Analogue Filters and Filtering Systems Venue of Conference: London, UK

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