|Title of host publication||International Conference on Field Programmable Logic and Applications, 2009 (FPL 2009), Prague|
|Publisher or commissioning body||Institute of Electrical and Electronics Engineers (IEEE)|
|Publication date||Aug 2009|
|Pages||423 - 428|
|Number of pages||5|
|Conference||International Conference on Field Programmable Logic and Applications|
|Period||1/08/09 → …|
This paper presents a reconfigurable processor designed to execute user-defined block-matching motion estimation algorithms, and a toolset for the design of such algorithms and for the configuration of the processor. The toolset enables the exploration of the processor's design space in order to find an optimal configuration depending on the target application. The use of the toolset to test different configurations for different kinds of video sequences is illustrated. Experimental results show the benefits and cost of certain optimizations in the motion estimation process, and that fast block-matching search algorithms can outperform full search algorithms commonly used in hardware implementations. The usefulness of the toolset in exploring the configuration space is also shown.
Rose publication type: Conference contribution
Additional information: With accompanying conference presentation
Sponsorship: The authors gratefully acknowledge the support obtained from the UK EPSRC under grant number EP/E062164/1.
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International Conference on Field Programmable Logic and Applications
|Duration||1 Aug 2009 → …|