A method is presented for reducing the implementation cost of a complex digital filter structure such as that used for IQ processing in adaptive equalisation. It is shown that the number of real filter sections required can be reduced from four to three at the expense of an increase in external addition stages from two to three (or five if coefficient additions are included). The approach is applicable to both LTE and DFE structures and results in savings which approach 25% for most practical cases.
Rose publication type: Journal article
- adaptive filters, equalisers