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Fully pipelined bloom filter architecture

Research output: Contribution to journalArticle

  • M Paynter
  • T Koçak
Original languageEnglish
Pages855 - 857
Number of pages3
JournalIEEE Communications Letters
Journal publication dateNov 2008
Journal issue11
Volume12
DOIs
StatePublished

Abstract

Recently, we proposed a two-stage pipelined Bloom filter architecture to save power for network security applications. In this letter, we generalize the pipelined Bloom filter architecture to k-stage and show that significant power savings can be achieved by employing one hash function per stage. We analytically show that the expected power consumption and latency of the fully pipelined Bloom filter architecture will not be greater than that of the two hash functions and two clock cycles, respectively, however large the number of hash functions is. Furthermore, we discuss the worst-case performance of the proposed architecture

Additional information

Publisher: IEEE Rose publication type: Journal article Terms of use: Copyright © 2008 IEEE. Reprinted from IEEE Communications Letters. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

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Research areas

  • bloom filters, network intrusion detection, low-power design

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