|Title of host publication||Unknown|
|Publisher or commissioning body||Institute of Electrical and Electronics Engineers (IEEE)|
|Publication date||May 1994|
|Pages||93 - 96|
|Number of pages||3|
|Conference||International Symposium on Circuits and Systems|
|Period||1/05/94 → …|
This paper introduces a method for optimising digital filter realisations at the gate level. The method is based on a derivative of the primitive operator approach of Bull and Horrocks which is extended using a carry-save decomposition of the primitive operator graph. This facilitates the generation of a set of Boolean expressions for the multiply-accumulate section of the filter which can be minimised using standard sum of products or Reed Muller techniques. The technique is fully described and results are presented for a representative range of FIR filters. Savings of up to 83% are obtained for sum-of-products minimisation when compared to a CSD coded hard-wired multiplier solution. Initial results suggest further improvements in excess of 20% for the Reed Muller case
Conference Proceedings/Title of Journal: Proc. 1994 IEEE Int. Sym. on Circuits and Systems
Rose publication type: Conference contribution
Sponsorship: The authors would like to express their thanks to Nigel Lester of the Department of Electrical and Electronic Engineering at
the University of Bristol for his assistance in producing the logic minimisation results presented here
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International Symposium on Circuits and Systems
|Duration||1 May 1994 → …|