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Professor David MayF.R.S.

Professor of Computer Science

1 - 10 out of 66Page size: 10
  1. 2017
  2. Published

    A Benes̆ Based NoC Switching Architecture for Mixed Criticality Embedded Systems

    Kerrison, S., May, D. & Eder, K., Jan 2017, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC 2016): Proceedings of a meeting held 21-23 September 2016, Lyon, France. Institute of Electrical and Electronics Engineers (IEEE), p. 125-132 8 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  3. 2016
  4. Published
  5. 2015
  6. Published

    Synchronising groups of threads with dedicated hardware logic

    May, D., 24 Feb 2015, Patent No. US 8,966,488

    Research output: Patent

  7. 2014
  8. Published
  9. 2012
  10. Published

    Emulating a large memory sequential machine with a collection of small memory ones

    Hanlon, J., Hollis, S. J. & May, D., 3 Oct 2012, In : arXiv. 1210.1158, 1210.1158.

    Research output: Contribution to journalArticle

  11. Published

    Scalable data abstractions for distributed parallel computations

    Hanlon, J., Hollis, S. J. & May, D., 3 Oct 2012, In : arXiv. 1210.1157.

    Research output: Contribution to journalArticle

  12. Published

    Interface processor

    May, D., 10 Jul 2012, IPC No. G06F 9/00 9/30, Patent No. US8219789

    Research output: Patent

  13. Published

    Processor communication tokens

    May, D., 17 Jun 2012, IPC No. G06F 15/16, Patent No. US8224884

    Research output: Patent

  14. Published
  15. Published

    Processor instruction set for controlling threads to respond to events

    May, D., 22 May 2012, IPC No. G06F 9/40, Patent No. US8185722

    Research output: Patent

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