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Design and implementation of a random neural network routing engine

Research output: Contribution to journalArticle

  • T Kocak
  • J Seeber
  • H Terzioglu
Original languageEnglish
Pages (from-to)1128 - 1143
Number of pages16
JournalIEEE Transactions on Neural Networks
Journal issue5
StatePublished - Sep 2003


Random neural network (RNN) is an analytically tractable spiked neural network model that has been implemented in software for a wide range of applications for over a decade. This paper presents the hardware implementation of the RNN model. Recently, cognitive packet networks (CPN) is proposed as an alternative packet network architecture where there is no routing table, instead the RNN based reinforcement learning is used to route packets. Particularly, we describe implementation details for the RNN based routing engine of a CPN network processor chip: the smart packet processor (SPP). The SPP is a dual port device that stores, modifies, and interprets the defining characteristics of multiple RNN models. In addition to hardware design improvements over the software implementation such as the dual access memory, output calculation step, and reduced output calculation module, this paper introduces a major modification to the reinforcement learning algorithm used in the original CPN specification such that the number of weight terms are reduced from 2n/sup 2/ to 2n. This not only yields significant memory savings, but it also simplifies the calculations for the steady state probabilities (neuron outputs in RNN). Simulations have been conducted to confirm the proper functionality for the isolated SPP design as well as for the multiple SPP's in a networked environment.

Additional information

Publisher: Institute of Electrical and Electronics Engineers (IEEE) Rose publication type: Journal article Sponsorship: The authors would like to thank A. Ejnioui for the fruitful discussions and the critical review of the paper, and D. Harper for his CAD tools assistance. Terms of use: Copyright © 2003 IEEE. Reprinted from IEEE Transactions on Neural Networks. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to By choosing to view this document, you agree to all provisions of the copyright laws protecting it.

    Research areas

  • network processors, neural network, random neural networks, packet switched networks

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