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Design of a novel delayed LMS decision feedback equaliser for HIPERLAN/1 FPGA implementation

Research output: Contribution to conferenceAbstract

Original languageEnglish
Pages300 - 304
StatePublished - May 1999


This paper presents the investigation of a new equaliser algorithm and architecture optimised for low cost FPGA implementation. The design was performed as part of the ESPRIT WINHOME project and is fully compliant with the European third generation HIPERLAN/1 wireless LAN standard. The equaliser supports GMSK modulation at an instantaneous transmission data-rate of just under 24 Mbits/s. In this paper the equaliser algorithm and pipelined DLMS DFE architecture is presented. Issues such as signal quantisation, bit and frame synchronisation and frequency offset correction are discussed in detail. The final structure is shown to achieve considerable hardware simplification together with improved performance when compared to a standard implementation of the complex LMS equaliser.

Additional information

Sponsorship: This work was performed as part of the ESPRIT WINHOME project (25048). Terms of use: Copyright © 1999 IEEE. Reprinted from Proceedings of IEEE Vehicular Technology Conference, Spring 1999. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Bristol's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to By choosing to view this document, you agree to all provisions of the copyright laws protecting it. Name of Conference: 49th Vehicular Technology Conference 1999 (VTC 1999-Spring) Venue of Conference: Houston, TX

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